CPU Microcode

2024-12-29T12:34:54Z

Arveex:

CPU '''microcode''' is a form of firmware that controls the processor's internals.

In modern processors, the microcode handles execution of complex and highly specialized instructions. Parts of the microcode also act as firmware for the processor's embedded controllers, and it is even used to fix or to mitigate '''processor design/implementation errata/bugs'''. Given the complexity of modern processors, a CPU may have over a hundred such errata.

Recently, microcode updates have become mandatory for security due to [https://en.wikipedia.org/wiki/Side-channel_attack side-channel attacks] against CPUs.

== Obtaining microcode updates on Alpine ==

{{Warning| Certain Intel CPUs, such Intel Atom with PSE errata, and Intel Haswell + Broadwell with TSX errata, can only be fixed via BIOS or UEFI update (which includes microcode); if you are using one of these CPUs, please do not use the instructions below}}

On Alpine Linux, CPU microcode is loaded early via initrd images, premade images are available from packages:

To obtain the microcode update package for AMD processors:
{{cmd|apk add {{pkg|amd-ucode}}}}

To obtain the microcode update package for Intel processors:
{{cmd|apk add {{pkg|intel-ucode}}}}

If you are using syslinux or grub in a typical setup, the packages will automatically append your {{path|extlinux.conf}} or {{path|grub.conf}} file and merely a reboot will be required to run the new microcode. Users using UEFI's built-in boot manager will have to use efibootmgr to add a second initrd line. Likewise if you are using the limine bootoader will need to add a 2nd MODULE_PATH directive in {{path|limine.cfg}} pointing to the ucode file.

== Verifying that the microcode image has loaded ==
Run the command:
{{cmd|dmesg | grep microcode}}
If the microcode initrd image was loaded, the microcode update driver will print a signature and revision

Example for Intel:
<pre>
[ 2.198775 ] microcode: sig=0x6fd, pf=0x80, revision=0xa4
</pre>

Example for AMD:
<pre>
[ 11.442146] microcode: Current revision: 0x0a0011d5
[ 11.447027] microcode: Updated early from: 0x0a0011d3
</pre>

{{Todo|Example needed for VIA CPUs, they seem to print slightly differently.}}
[[Category:Security]]

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CPU Microcode